Gate-all-around (GAA) nanosheet (NS) field effect transistors (FETs) formed according to conventional methods have an integration difficulty of simultaneously forming source-drain (SD) stressor regions while also achieving low gate-drain capacitance (Cgd). Conventional GAA NS FETs are formed with dielectric internal spacers at the SD boundary. These dielectric internal spacers are conventionally formed after a task of etching to form recesses for SD electrodes, but prior to a task of forming the SD electrodes in the recesses (i.e., dielectric internal spacers are conventionally formed post-SD recess etch and pre-SD epitaxial refill). Accordingly, when the epitaxial SD material is grown to form the SD regions according to these conventional methods, defects form at the dielectric/channel interface, which creates defective SD regions resulting in non-strained SD regions (i.e., no SD stressor regions).
Conventional GAA NS FETs have a further integration difficulty of achieving multiple threshold voltage (mVt) architecture while also achieving low Cgd. Conventional GAA NS FETs are formed by a gate stack (i.e., a dielectric material and a metal) wrapped around each semiconductor channel layer (i.e., each nanosheet channel layer), with the channel layers separated by a vertical spacing (VSP) distance. To achieve mVt integration, the VSP may be increased to more easily enable different metal layers to be formed in the VSP region, which enables different Vt values. However, increasing VSP correspondingly increases Cgd.
Conventional GAA NS FETs have a further integration difficulty of achieving uniform channel layer thickness for wide width channel layers. Conventional GAA NS FETs are formed by an alternating stack of sacrificial layers and channel layers overlying a substrate. During a replacement metal gate (RMG) task, the sacrificial layers are removed selective to the channel layers. The channel layers may be silicon (Si) and the sacrificial layers may be silicon germanium (SiGe) with the Ge % being from approximately 25% to approximately 60%. However, if the Ge % is at the low end of the range (e.g., approximately 25%), the Si channel layers may also be etched during a task of removing the sacrificial layers by an undercut etch process. Etching the Si channel layers results in non-uniform channel layers which do not have the desired electrical properties, such as transport and Vt. For instance, during a conventional task of removing the sacrificial layers, the Si channel layers may also be partially removed (e.g., edges of the Si channel layers may be removed resulting in elliptical-shaped Si channel layers). On the other hand, if the Ge % is at the high end of the range (e.g., approximately 60% or greater), the selectively to Si is increased, but there is more diffusion of Ge into the adjacent channel layers (i.e., forming a broad transition region), such that the channel layers are formed of Si and Ge instead of Si only. Accordingly, providing the sacrificial layers with a Ge % at the high end of the range during conventional GAA NS FET fabrication results in a broad transition region and/or non-uniform channel thickness due to non-uniform diffusion of Ge into the adjacent channel layers.